Christos Papachristou
Department of EECS, Case School of Engineering
We have proposed a non-traditional reconfigurable processor that involves
four architecture Layers: (1) reconfigurable hardware fabric; (2) embedded
processors and memory; (3) real-time Operating system RTOS; (4) applications
manager. Reconfiguration strategy occurs at several levels: Following are
the major tasks of our work. (a) selection of application modules by the applications
manager; (b) mapping of modules into the hardware fabric or the embedded processors,
depending on data delivery and performance requirements; and(c) configuration
of the hardware fabric and the embedded processor to meet data delivery requirements.
The reconfigurable hardware is essential for mapping of wireless communications
algorithms such as: IR filtering, multichannel CDMA, complex encoding, advanced
imaging.
Technology Benefits
Core benefit: Design of Self reconfigurable processor communication node that
adapts to changing environment state. Reconfiguration is useful in two scenarios
forcommunications :
- quick modification of a processing transceiver node
- slower adaptation autonomously in the environment
Our overall goal is to develop a prototype self-reconfigurable communication
processor emulating wireless application algorithms.
Results
Our focus has been on Reconfigurable Hardware fabric layer. We have developed
two software tools for this purpose:
1) Binding Configuration Software (BCS). This tool uses an architecture resource
netlist as input and generates connectivity bindings within a given Hardware
fabric layer.
2) Architecture Mapper Software. This tool uses an algorithm data flow as
input and generates an arch resource netlist. We are also completing work
on Dynamic Configuration Mapping software.