JOURNAL PUBLICATIONS


Published/Accepted for Publication
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2014
Swarup Bhunia, Michael Hsiao, Mainak Banga, Seetharam Narasimhan, “Hardware Trojan Attacks: Threat Analysis and Countermeasures”, to appear in Proceedings of the IEEE (PIEEE), 2014.
Swaroop Ghosh, Abhishek Basak, and Swarup Bhunia, “How Secure Are Printed Circuit Boards Against Trojan Attacks?”, to appear in IEEE Design and Test of Computers (D&T) Magazine.
Xinmu Wang, Yu Zheng, Abhishek Basak and Swarup Bhunia, “IIPS: Infrastructure IP for SoC Security”, to appear in IEEE Transactions on Computers (TComp).
Somnath Paul, Aswin Krishna, Wenchao Qian, Robert Karam, and Swarup Bhunia, “MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications”, to appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
Yu Zheng, Xinmu Wang and Swarup Bhunia, “SACCI: Scan-based Characterization through Clock Phase Sweep for Counterfeit Chip Detection”, to appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
2013
Abhishek Basak, Vaishnavi Ranganathan and Swarup Bhunia, “Implantable Ultrasonic Imaging Assembly for Automated Monitoring of Internal Organs”, to appear in IEEE Transactions on Biomedical Circuits and Systems (TBioCAS).
Jongsun Park, Jangwon Park and Swarup Bhunia, “VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications”, to appear in IEEE Transactions on Circuits and Systems II (TCAS-II).
Anandaroop Ghosh, Somnath Paul, Jongsun Park, and Swarup Bhunia, “Improving Energy Efficiency in FPGA through Judicious Mapping of Computation to Embedded Memory Blocks”, to appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
2012
Seetharam Narasimhan, Wen Yueh, Xinmu Wang, Saibal Mukhopadhyay, and Swarup Bhunia, “Improving IC Security against Trojan Attacks through Integration of Security Monitors”, to appear in IEEE Design & Test of Computers (D&T) Special Issue on Smart Silicon.
Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis Wolff, Christos Papachristou, Kaushik Roy, and Swarup Bhunia, “Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis”, to appear in IEEE Transactions on Computers (TC).
Swarup Bhunia, Miron Abramovici, Dakshi Agarwal, Paul Bradley, Michael S. Hsiao, Jim Plusquellic, and Mohammad Tehranipoor, “Protection against Hardware Trojan Attacks: Towards a Comprehensive Solution”, to appear in IEEE Design & Test of Computers (D&T).
Seetharam Narasimhan, Keerthi Kunaparaju, and Swarup Bhunia, “Healing of DSP Circuits under Power Bound Using Post-Silicon Operand Bitwidth Truncation”, to appear in IEEE Transactions on Circuits and Systems I (TCAS-I).
Somnath Paul, Saibal Mukhopadhyay and Swarup Bhunia, “A Variation-Aware Preferential Design Approach for Memory Based Reconfigurable Computing”, to appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
2011
Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia, “Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) Special Issue on Advances in Design of Energy-Efficient Circuits and Systems, vol, 1, no. 3, pp. 369-380, 2011. [Abstract] [Full Text: PDF pdf]
Rajat Subhra Chakraborty and Swarup Bhunia, “Security Against Hardware Trojan Attacks Using Key-based Design Obfuscation”, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 27. no. 6, pp. 767-785, Dec 2011. [Abstract] [Full Text: PDF pdf]
Seetharam Narasimhan, Rajat Subhra Chakraborty and Swarup Bhunia, “Hardware IP Protection during Evaluation Using Embedded Sequential Trojan”, IEEE Design & Test of Computers (D&T), vol. PP, no. 99, pp. 1-9, 2011. [Abstract] [Full Text: PDF pdf]
Seetharam Narasimhan, Hillel Chiel and Swarup Bhunia, “Ultra Low-Power and Robust Digital Signal Processing Hardware for Implantable Neural Interface Microsystems”, IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), vol. 5, no. 2, pp. 169-178, April 2011. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Fang Cai, Xinmiao Zhang and Swarup Bhunia, "Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache", IEEE Transactions on Computers (TC) Special Issue on Dependable Computer Architecture, vol. 60, no. 1, pp. 20-34, Feb 2011. [Abstract] [Full Text: PDF pdf]
Somnath Paul and Swarup Bhunia, "Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 19, no. 8, pp. 1368-1379, 2011. [Abstract] [Full Text: PDF pdf]
2010
Te-Hao Lee, Swarup Bhunia, and Mehran Mehregany, “Electromechanical Computing at 500°C with Silicon Carbide”, Science, vol. 329, no. 5997, pp. 1316-1318, Sep. 2010. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Saibal Mukhopadhyay and Swarup Bhunia, "Circuit and Architecture Co-design Approach for Hybrid CMOS-STTRAM Non-volatile FPGA",  IEEE Transactions on Nanotechnology (TNANO), vol. 10, no. 3, pp. 385-394, 2010. [Abstract] [Full Text: PDF pdf]
Somnath Paul and Swarup Bhunia, "A Scalable Memory-based Reconfigurable Computing Framework for Nanoscale Crossbar", IEEE Transactions on Nanotechnology (TNANO), vol. pp, no. 99, pp. 1-10, 2010. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Hamid Mahmoodi and Swarup Bhunia, "Low-Overhead Fmax Calibration at Multiple Operating Points Using Delay Sensitivity Based Path Selection", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 15, no. 2, Feb 2010. [Abstract] [ Full Text: PDF pdf]
Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, "Trifecta: A Non-Speculative Scheme to Exploit Common, Data-Dependent Subcritical Paths",  IEEE Trans. on Very Large Scale Integration Systems (TVLSI), vol. 18, no. 1, pp. 53-65, Jan. 2010. [Abstract] [Full Text: PDF pdf]
2009
Rajat Subhra Chakraborty and Swarup Bhunia, “A Study of Asynchronous Design Methodology for Robust CMOS-Nano Hybrid System Design”, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 5, no. 3, pp. 12:1-12:22, Aug 2009. [Abstract] [ Full Text: PDF pdf]
Rajat Subhra Chakraborty and Swarup Bhunia, "HARPOON: An Obfuscation based SoC Design Methodology for Hardware Protection",  IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493-1502, Sep. 2009. [Abstract] [ Full Text: PDF pdf]
Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou and Swarup Bhunia, "Low-Power Hybrid CMOS-NEMS FPGA: Circuit Level Analysis and Defect-Aware Mapping",  IET Computers and Digital Techniques (IETCDT), vol. 3, no. 6, pp. 609-624, Nov. 2009. [Abstract] [ Full Text: PDF pdf]
2008
Patrick Ndai, Swarup Bhunia, Amit Agarwal and Kaushik Roy, "Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput", IEEE Transactions on Computers, vol. 57, no. 7, pp. 940-951, July 2008.[Abstract] [Full Text: PDF pdf]
Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury and Kaushik Roy, "Arbitrary Two-Pattern Delay Testing Using A Low-Overhead Supply Gating Technique", Journal of Electronic Testing: Theory and Applications (JETTA), vol. 24, no. 6, pp. 577-590, June 2008. [Abstract] [Full Text: PDF pdf]
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, and Kaushik Roy, "Profit Aware Circuit Design under Process Variations Considering Speed Binning", IEEE Trans. on Very Large Scale Integration Systems, vol. 16, no. 7, pp. 806-815, July 2008. [Abstract] [Full Text: PDF pdf]
2007
Rajat Subhra Chakraborty, Seetharam Narasimhan and Swarup Bhunia, "Hybridization of CMOS with CNT-Based Nano Electromechanical Switch for Low Leakage and Robust Circuit Design", IEEE Trans. on Circuits and Systems, vol. 54, no. 7, pp. 2480-2488, Nov. 2007. [Abstract] [Full Text: PDF pdf]
Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, "Low-Power and Testable Circuit Synthesis Using Shannon Decomposition", ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 12, no. 4, pp. 47:1-47:6, Sep. 2007. [Abstract] [Full Text: PDF pdf]
Amit Agarwal, Kunhyuk Kang, Swarup Bhunia and Kaushik Roy, "Device-Aware Yield-Centric Dual-Vt Design under Parameter Variations in Nano-Scale Technologies", IEEE Trans. on Very Large Scale Integration Systems, vol. 15, no. 6, pp. 660-671, June 2007. [Abstract] [Full Text: PDF pdf]
Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, "CRISTA: A New Paradigm for Low-power, Variation-Tolerant and Adaptive Circuit Synthesis Using Critical Path Isolation", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pp. 1947-1956, Nov. 2007. [Abstract] [Full Text: PDF pdf]
2006
Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, “Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis”, IEEE Trans. on Very Large Scale Integration Systems, vol. 14, no. 9, pp. 1034-1039, 2006. [Abstract] [Full Text: PDF pdf]
Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, "A Novel Delay Fault Testing Methodology Using Low Overhead Built-In Delay Sensor", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2934-2943, Dec. 2006. [Abstract] [Full Text: PDF pdf]
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay and Kaushik Roy, "Delay Modeling and Statistical Design of Pipelined Circuit under Process Variation", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2427-2436, Nov. 2006. [Abstract] [Full Text: PDF pdf]
Saibal Mukhopadhyay, Swarup Bhunia and Kaushik Roy, “Modeling and Analysis of Loading Effect on Leakage of Nanoscaled Bulk-CMOS Logic Circuits”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 25, no.8, pp. 1486-1495, 2006. [Abstract] [Full Text: PDF pdf]
2005
Arijit Raychowdhury, Bipul Paul, Swarup Bhunia and Kaushik Roy, “Computing with Sub-threshold Leakage: Device/Circuit/Architecture Co-design for Ultralow-power Subthreshold Operation”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 13, no. 11, pp. 1213-1224, 2005. [Abstract] [Full Text: PDF pdf]
Qikai Chen, Hamid Mahmoodi, Swarup Bhunia and Kaushik Roy, “Efficient testing of SRAM with optimized March sequences and a Novel DFT Technique for emerging failures due to process variations”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 13, no. 11, pp. 1286-1295, 2005. [Abstract] [Full Text: PDF pdf]
Swarup Bhunia and Kaushik Roy, “A novel wavelet transform-based transient current analysis for fault detection and localization”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 13, no. 4, pp. 503-507, 2005. [Abstract] [Full Text: PDF pdf]
Swarup Bhunia, Animesh Datta, Nilanjan Banerjee and Kaushik Roy, “GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks”, IEEE Transactions on Computers (TC), vol. 54, no. 6, pp. 752-766, 2005. [Abstract] [Full Text: PDF pdf]
Swarup Bhunia, Hamid Mahmoodi, Saibal Mukhopadhyay, Debjyoti Ghosh and Kaushik Roy, “Low-Power Scan Design Using First Level Supply Gating”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 13, no. 3, pp. 384-395, 2005. [Abstract] [Full Text: PDF pdf]
Swarup Bhunia, Arijit Roychowdhury and Kaushik Roy, “Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current”, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 21, no. 3, pp. 243-255, 2005. [Abstract] [Full Text: PDF pdf]
Lih-yih Chiou, Swarup Bhunia and Kaushik Roy, “Synthesis of Application-Specific Highly Efficient Multi-Mode Cores for Embedded Systems”, ACM transactions on Embedded Computing System (TECS), vol. 4, no. 1, pp. 168-188, 2005. [Abstract] [Full Text: PDF pdf]
Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, “Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current”, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 21, no. 2, pp. 147-159, 2005. [Abstract] [Full Text: PDF pdf]
2004
Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy and T. N. Vijaykumar, “DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 12, no. 3, pp. 245-254, 2004. [Abstract] [Full Text: PDF pdf]